IS61VPS51236价格

参考价格:¥111.3304

型号:IS61VPS51236A-200TQLI 品牌:ISSI 备注:这里有IS61VPS51236多少钱,2025年最近7天走势,今日出价,今日竞价,IS61VPS51236批发/采购报价,IS61VPS51236行情走势销售排行榜,IS61VPS51236报价。
型号 功能描述 生产厂家 企业 LOGO 操作

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

Synchronous SRAM

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

封装/外壳:165-TBGA 包装:托盘 描述:IC SRAM 18MBIT PARALLEL 165TFBGA 集成电路(IC) 存储器

ETC

知名厂家

封装/外壳:165-TBGA 包装:卷带(TR) 描述:IC SRAM 18MBIT PARALLEL 165TFBGA 集成电路(IC) 存储器

ETC

知名厂家

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

IS61VPS51236产品属性

  • 类型

    描述

  • 型号

    IS61VPS51236

  • 功能描述

    静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,165 Ball BGA

  • RoHS

  • 制造商

    Cypress Semiconductor

  • 存储容量

    16 Mbit

  • 组织

    1 M x 16

  • 访问时间

    55 ns

  • 电源电压-最大

    3.6 V

  • 电源电压-最小

    2.2 V

  • 最大工作电流

    22 uA

  • 最大工作温度

    + 85 C

  • 最小工作温度

    - 40 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    TSOP-48

  • 封装

    Tray

更新时间:2025-12-12 13:31:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ISSI
19+
QFP
8550
ISSI/芯成
24+
BGA165
60000
ISSI
24+
BGA
20000
全新原厂原装,进口正品现货,正规渠道可含税!!
2406+
QFP-100
650
诚信经营!进口原装!量大价优!
ISSI, Integrated Silicon Solut
21+
BGA
1000
进口原装!长期供应!绝对优势价格(诚信经营
ISSI
1322+
BGA
91
一级代理,专注军工、汽车、医疗、工业、新能源、电力
ISSI
QFP100
800
正品原装--自家现货-实单可谈
ISSI
24+
n/a
25836
新到现货,只做原装进口
ISSI
25+
QFP
4500
原装正品!公司现货!欢迎来电!
23+
BGA
64936
##公司主营品牌长期供应100%原装现货可含税提供技术

IS61VPS51236数据表相关新闻