型号 功能描述 生产厂家 企业 LOGO 操作
IS61LPS51236B

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

IS61LPS51236B

Internal self-timed write cycle

文件:1.91707 Mbytes Page:33 Pages

ISSI

矽成半导体

IS61LPS51236B

Synchronous SRAM

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

封装/外壳:165-TBGA 包装:卷带(TR) 描述:IC SRAM 18MBIT PARALLEL 165TFBGA 集成电路(IC) 存储器

ETC

知名厂家

封装/外壳:100-LQFP 包装:托盘 描述:IC SRAM 18MBIT PARALLEL 100LQFP 集成电路(IC) 存储器

ETC

知名厂家

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

文件:220.58 Kbytes Page:34 Pages

ISSI

矽成半导体

256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

文件:375.56 Kbytes Page:35 Pages

ISSI

矽成半导体

更新时间:2025-11-23 23:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ISSI(美国芯成)
24+
LQFP100(14x20)
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
ISSI, Integrated Silicon Solut
23+
100-LQFP
3500
只做原装,假一赔十
ISSI
2
ISSI(美国芯成)
2447
TFBGA-165(13x15)
315000
144个/托盘一级代理专营品牌!原装正品,优势现货,长
ISSI
24+
n/a
25836
新到现货,只做原装进口
ISSI
21+
TQFP100
200
一级代理,专注军工、汽车、医疗、工业、新能源、电力
ISSI
2025+
LQFP
5000
原装进口价格优 请找坤融电子!
ISSI, Integrated Silicon Solut
21+
64-LBGA
5280
进口原装!长期供应!绝对优势价格(诚信经营
ISSI
23+
TQFP100
50000
全新原装正品现货,支持订货
ISSI
25+
电联咨询
7800
公司现货,提供拆样技术支持

IS61LPS51236B数据表相关新闻