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型号	功能描述	生产厂家企业	LOGO
IS61LF204836B	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B	Synchronous SRAM	ISSI 矽成半导体	ISSI
IS61LF204836B_V01	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B2	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B2I	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B2I	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B2L	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B2L	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B2LI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B2LI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3I	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3I	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3L	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3L	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3LI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3LI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5M3	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5M3	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5M3I	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5M3L	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5M3LI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5TQ	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5TQI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5TQL	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5TQLI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5B2	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5B2I	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5B2L	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5B2LI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5B3	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5B3I	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5B3L	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5B3LI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5M3	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5M3I	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5M3L	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5M3LI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5TQ	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5TQI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5TQL	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-7.5TQLI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B2	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B2I	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B2L	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B2LI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3I	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3L	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5B3LI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5M3	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5M3I	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5M3L	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5M3LI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5TQ	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5TQI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5TQL	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI
IS61LF204836B-6.5TQLI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM 文件：1.68486 Mbytes Page：34 Pages	ISSI 矽成半导体	ISSI

IS61LF204836B产品属性

类型
描述
型号
IS61LF204836B
制造商
ISSI
制造商全称
Integrated Silicon Solution, Inc
功能描述
2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

IS61LF204836B供应商更多...

更新时间：2025-12-10 23:00:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市高捷芯城科技有限公司	IS61LF204836B-7.5TQLI-TR	ISSI(美国芯成)	24+	LQFP100(14x20)	7350	现货供应,当天可交货!免费送样,原厂技术支持!!!	询价
深圳市赛美科科技有限公司	IS61LF25618A-7.5TQLI	ISSI		QFP	5350	一级代理原装正品假一罚十价格优势长期供货	询价
千层芯半导体(深圳)有限公司	IS61LF25618A-7.5TQLI	ISSI	24+	QFP	30617	主打ISSI品牌价格绝对优势	询价
深圳市科恒伟业电子有限公司	IS61LF204836B-7.5TQLI	ISSI/芯成	2450+	TQFP	8850	只做原装正品假一赔十为客户做到零风险!!	询价
深圳市毅创腾电子科技有限公司	IS61LF25618A-7.5TQLI	ISSI	23+	100-TQFP(14x20)	7050	专业分销产品!原装正品!价格优势!	询价
深圳市冠亿通科技有限公司	IS61LF204836B-7.5TQLI-TR	ISSI,	25+		25000	原厂原包深圳现货主打品牌假一赔百可开票!	询价
深圳市河锋鑫科技有限公司	IS61LF204836B7.5TQLITR	ISSI Integrated Silicon Soluti	22+	100LQFP (14x20)	9000	原厂渠道,现货配单	询价
齐创科技(上海,北京,青岛)有限公司	IS61LF25618A-7.5TQI	ISSI	23+	TQFP	5000	原装正品,假一罚十	询价
深圳市赛尔通科技有限公司	IS61LF25618A-7.5TQLI	ISSI	23+	100-TQFP	65480		询价
天津市博通航睿技术有限公司	IS61LF25618A-7.5TQI	ISSI	23+	TQFP	7000		询价

IS61LF204836B芯片相关品牌

IS61LF204836B规格书下载地址

IS61LF204836B参数引脚图相关

IS61LF204836B数据表相关新闻

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IS61LV256AH-15JI，IS61LV256AH-10T，IS61LV256AH-10TI，IS61LV256AH-12J，IS61LV2568L-12TI，IS61LV2568L-10TLI，IS61LV2568L-10K，IS61LV2568-12T，IS61LV2568-12K，IS61LV2568-15T
IS61LV256AH-15JI，IS61LV256AH-10T，IS61LV256AH-10TI，IS61LV256AH-12J，IS61LV2568L-12TI，IS61LV2568L-10TLI，IS61LV2568L-10K，IS61LV2568-12T，IS61LV2568-12K，IS61LV2568-15T
2020-1-1

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IS61LF204836B产品属性

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IS61LV256AH-15JI，IS61LV256AH-10T，IS61LV256AH-10TI，IS61LV256AH-12J，IS61LV2568L-12TI，IS61LV2568L-10TLI，IS61LV2568L-10K，IS61LV2568-12T，IS61LV2568-12K，IS61LV2568-15T

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