32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

256Mb SYNCHRONOUS DRAM

文件：1.23822 Mbytes Page：63 Pages

SDR SDRAM

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

封装/外壳：54-TFBGA 包装：卷带（TR） 描述：IC DRAM 256MBIT PARALLEL 54TFBGA 集成电路（IC） 存储器

封装/外壳：54-TSOP（0.400"，10.16mm 宽） 包装：托盘 描述：IC DRAM 256MBIT PAR 54TSOP II 集成电路（IC） 存储器

256 Mb Single Data Rate Synchronous DRAM

文件：1.59869 Mbytes Page：40 Pages

32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

文件：1.05062 Mbytes Page：63 Pages

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

文件：942.97 Kbytes Page：63 Pages