512K x 32Bits x 4Banks Mobile DDR SDRAM

Features • JEDEC standard 1.8V power supply. • VDD = 1.8V, VDDQ = 1.8V • Four internal banks for concurrent operation • MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave) • Fully differential clock inputs (CK,

512K x 32Bits x 4Banks Mobile DDR SDRAM

Features • JEDEC standard 1.8V power supply. • VDD = 1.8V, VDDQ = 1.8V • Four internal banks for concurrent operation • MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave) • Fully differential clock inputs (CK,

封装/外壳：90-TFBGA 包装：卷带（TR） 描述：IC DRAM 64MBIT PARALLEL 90TFBGA 集成电路（IC） 存储器

动态随机存取存储器 64M, 1.8V, M-DDR 2Mx32, 166Mhz, RoHS

动态随机存取存储器 64M, 1.8V, M-DDR 2Mx32, 166Mhz, RoHS

封装/外壳：90-TFBGA 包装：托盘 描述：IC DRAM 64MBIT PARALLEL 90TFBGA 集成电路（IC） 存储器