CMOS 8/16-Bit Microprocessor

Description The Intersil 80C88 high performance 8/16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the

CMOS 8/16-Bit Microprocessor

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CMOS 8-/16-Bit Microprocessor

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封装/外壳：40-DIP（0.600"，15.24mm） 包装：管件 描述：IC MPU 80C88 8MHZ 40DIP 集成电路（IC） 微处理器

CMOS 8/16-Bit Microprocessor

Description The Intersil 80C88 high performance 8/16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the

CMOS 8/16-Bit Microprocessor

Description The Intersil 80C88 high performance 8/16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the

CMOS 8/16-Bit Microprocessor

Description The Intersil 80C88 high performance 8/16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the

CMOS 8/16-Bit Microprocessor

Description The Intersil 80C88 high performance 8/16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the

CMOS 8/16-Bit Microprocessor

Description The Intersil 80C88 high performance 8/16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the