Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS

The IN74HC75A is identical in pinout to the LS/ALS75. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 2-bit transparent latches and can be used as temporary storage for binary i

Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS

The IN74HC75A is identical in pinout to the LS/ALS75. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 2-bit transparent latches and can be used as temporary storage for binary i

Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS

Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS

The IN74HC75A is identical in pinout to the LS/ALS75. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 2-bit transparent latches and can be used as temporary storage for binary i

Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS

The IN74HC75A is identical in pinout to the LS/ALS75. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 2-bit transparent latches and can be used as temporary storage for binary i

Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS

The IN74HC75A is identical in pinout to the LS/ALS75. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 2-bit transparent latches and can be used as temporary storage for binary i

Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS

The IN74HC75A is identical in pinout to the LS/ALS75. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 2-bit transparent latches and can be used as temporary storage for binary i

Quad Bistable Latch

Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

4 BIT D TYPE LATCH

DESCRIPTION The M74HC75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED : tPD = 11ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL

4 BIT D TYPE LATCH

DESCRIPTION The M54/74HC75 is a high speed CMOS 4-BIT D-TYPE LATCH fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 10 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 VCC (MIN.) ■ OUTPUT

4 BIT D TYPE LATCH

DESCRIPTION The M74HC75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED : tPD = 11ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL