Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

Quad bistable transparant latch

Quad bistable transparant latch

1. General description The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs foll

Quad bistable transparent latch

The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as l • Complementary Q and Q outputs\n• VCC and GND on the center pins\n• Low-power dissipation\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC75: CMOS level\n\n• ESD protection:• HBM EIA/JESD22-A114F exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• ;

74HC75DB - Quad bistable transparent latch

Quad bistable transparent latch - The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ output ·Complementary Q and Q outputs\n·VCC and GND on the center pins\n·Low-power dissipation\n·Complies with JEDEC standard no. 7A\n·Input levels:·For 74HC75: CMOS level;

Quad bistable transparant latch

Quad bistable transparant latch

The 74HC75-Q100 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD)

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC LATCH QUAD BISTABLE 16SOIC 集成电路（IC） 锁存器

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC QUAD BIST TRANSP LATCH 16SSOP 集成电路（IC） 锁存器

Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

4 BIT D TYPE LATCH

DESCRIPTION The M74HC75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED : tPD = 11ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL

4 BIT D TYPE LATCH

DESCRIPTION The M54/74HC75 is a high speed CMOS 4-BIT D-TYPE LATCH fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 10 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 VCC (MIN.) ■ OUTPUT

4 BIT D TYPE LATCH

DESCRIPTION The M74HC75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED : tPD = 11ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL