Dual 1-of-4 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS

Dual 1-of-4 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS The IN74HC139A is identical in pinout to the LS/ALS139. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 1-o

Dual 1-of-4 Decoder/Demultiplexer

The IN74HC139A is identical in pinout to the LS/ALS139. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 1-of-4 decoders, each of which decodes a two-bit Address to one-of-four a

Dual 1-of-4 Decoder/Demultiplexer

Dual 1-of-4 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS

Dual 1-of-4 Decoder/Demultiplexer

The IN74HC139A is identical in pinout to the LS/ALS139. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 1-of-4 decoders, each of which decodes a two-bit Address to one-of-four a

Dual 1-of-4 Decoder/Demultiplexer

The IN74HC139A is identical in pinout to the LS/ALS139. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 1-of-4 decoders, each of which decodes a two-bit Address to one-of-four a

Dual 1-of-4 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS139.

High Speed CMOS Logic

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High Speed CMOS Logic

文件：696.19 Kbytes Page：6 Pages