Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS139.

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

74系列 逻辑芯片

High Speed CMOS Logic

文件：641.19 Kbytes Page：6 Pages

High Speed CMOS Logic

文件：696.19 Kbytes Page：6 Pages

Dual 2-to-4 line decoder/demultiplexer

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS139.

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

Dual 2-to-4 line decoder/demultiplexer

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

Dual 2-to-4 line decoder/demultiplexer

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input f

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

Dual 2-to-4 line decoder/demultiplexer

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input f

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input f

High Speed CMOS Logic

文件：696.19 Kbytes Page：6 Pages

Dual 2-to-4 line decoder/demultiplexer

74HC CMOS logic IC series

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1 X 2:4 16SO 集成电路（IC） 信号开关，多路复用器，解码器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1 X 2:4 16SO 集成电路（IC） 信号开关，多路复用器，解码器

Dual 2-to-4 line decoder/demultiplexer

文件：762.31 Kbytes Page：18 Pages

Dual 2-to-4 line decoder/demultiplexer

文件：762.31 Kbytes Page：18 Pages

Dual 2-to-4 line decoder/demultiplexer

文件：762.31 Kbytes Page：18 Pages

Dual 2-to-4 line decoder/demultiplexer

文件：762.31 Kbytes Page：18 Pages