Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. • Output

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. • Output

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs.• Outputs Direct

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. • Output

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs.• Outputs Direct

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. • Output

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. • Output

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. • Output

4-Bit Synchronous Binary Up/Down Counter

The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs.• Outputs Direct

Dual JK Negative Edge-Triggered Flip-Flop

Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will p

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

Dual J-K Flip Flop with Preset and Clear The TC74AC112 is an advanced high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low pow

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：331.08 Kbytes Page：6 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：331.08 Kbytes Page：6 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：331.08 Kbytes Page：6 Pages