28-BIT 1:2 REGISTERED BUFFER WITH PARITY

Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM lo

28-BIT 1:2 REGISTERED BUFFER WITH PARITY

Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSGateEN and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 160-ball LFBGA package Applic

28-BIT 1:2 REGISTERED BUFFER WITH PARITY

Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSGateEN and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 160-ball LFBGA package Applic

28-BIT 1:2 REGISTERED BUFFER WITH PARITY

Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM lo

封装/外壳：160-LFBGA 包装：管件 描述：IC BUFFER 28BIT 1:2 REG 160-BGA 集成电路（IC） 专用逻辑器件

封装/外壳：160-LFBGA 包装：管件 描述：IC BUFFER 28BIT 1:2 REG 160-BGA 集成电路（IC） 专用逻辑器件