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IDT74LVC价格
参考价格:¥1.3000
型号:IDT74LVC125APWR 品牌:TEXAS 备注:这里有IDT74LVC多少钱,2026年最近7天走势,今日出价,今日竞价,IDT74LVC批发/采购报价,IDT74LVC行情走势销售排行榜,IDT74LVC报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: The LVC16244A 16-bit buffer/driver is built using advanced dual metal CMOS technology. The LVC16244A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be u | IDT | |||
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: The LVC16244A 16-bit buffer/driver is built using advanced dual metal CMOS technology. The LVC16244A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be u | IDT | |||
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: The LVC16244A 16-bit buffer/driver is built using advanced dual metal CMOS technology. The LVC16244A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be u | IDT | |||
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: The LVC16244A 16-bit buffer/driver is built using advanced dual metal CMOS technology. The LVC16244A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be u | IDT | |||
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: The LVC16244A 16-bit buffer/driver is built using advanced dual metal CMOS technology. The LVC16244A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be u | IDT | |||
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: This 16-bit bus transceiver is built using advanced dual metal CMOS technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and Output Enable controls are designed to operate this device as either two inde | IDT | |||
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: This 16-bit bus transceiver is built using advanced dual metal CMOS technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and Output Enable controls are designed to operate this device as either two inde | IDT | |||
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: This 16-bit bus transceiver is built using advanced dual metal CMOS technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and Output Enable controls are designed to operate this device as either two inde | IDT | |||
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: This 16-bit bus transceiver is built using advanced dual metal CMOS technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and Output Enable controls are designed to operate this device as either two inde | IDT | |||
3.3V CMOS ONE-TO-FOUR ADDRESS/CLOCK DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS ONE-TO-FOUR ADDRESS/CLOCK DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS ONE-TO-FOUR ADDRESS/CLOCK DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS ONE-TO-FOUR ADDRESS/CLOCK DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS ONE-TO-FOUR ADDRESS/CLOCK DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: The LVC16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. The LVC16373A can be used for implement ing memory address latches, I/O ports, and bus drivers. The Output Enab | IDT | |||
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: The LVC16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. The LVC16373A can be used for implement ing memory address latches, I/O ports, and bus drivers. The Output Enab | IDT | |||
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: The LVC16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. The LVC16373A can be used for implement ing memory address latches, I/O ports, and bus drivers. The Output Enab | IDT | |||
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: The LVC16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. The LVC16373A can be used for implement ing memory address latches, I/O ports, and bus drivers. The Output Enab | IDT | |||
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: The LVC373A Octal transparent D-type latch is built using advanced dual metal CMOS technology. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. FEATURES: | IDT | |||
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: The LVC373A Octal transparent D-type latch is built using advanced dual metal CMOS technology. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. FEATURES: | IDT | |||
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: The LVC373A Octal transparent D-type latch is built using advanced dual metal CMOS technology. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. FEATURES: | IDT | |||
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: The LVC373A Octal transparent D-type latch is built using advanced dual metal CMOS technology. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. FEATURES: | IDT | |||
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: The LVC373A Octal transparent D-type latch is built using advanced dual metal CMOS technology. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. FEATURES: | IDT | |||
CMOS OCTAL BUS TRANSCEIVER AND 3.3V TO 5V SHIFTER WITH 3-STATE OUT-PUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: The LVC4245A is manufactured using advanced dual metal CMOS technology. This octal noninverting bus transceiver contains two separate supply rails; B port has VCCB, which is set at 3.3V, and A port has VCCA, which is set at 5V. This allows for translation from a 3.3V to a 5V environm | IDT | |||
3.3V CMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: The LVC541A octal buffer/driver is built using advanced dual metal CMOS technology. This device is ideal for driving bus lines or buffer memory address registers. This device features inputs and outputs on opposite sides of the package that facilitate printed circuit board layout. Th | IDT | |||
3.3V CMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • Rail-to-rail output swing for increased noise ma | RENESAS 瑞萨 | |||
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, AND BUS-HOLD FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to | RENESAS 瑞萨 | |||
3.3V CMOS HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS AND 5 VOLT TOLERANT I/O 文件:54.06 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS AND 5 VOLT TOLERANT I/O 文件:54.06 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS AND 5 VOLT TOLERANT I/O 文件:54.06 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS AND 5 VOLT TOLERANT I/O 文件:54.06 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O 文件:56.78 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O | RENESAS 瑞萨 | |||
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O 文件:56.78 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O 文件:56.78 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O 文件:56.78 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS TRIPLE 3-INPUT AND GATE WITH 5 VOLT TOLERANT I/O 文件:55.56 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS TRIPLE 3-INPUT AND GATE WITH 5 VOLT TOLERANT I/O | RENESAS 瑞萨 | |||
3.3V CMOS TRIPLE 3-INPUT AND GATE WITH 5 VOLT TOLERANT I/O 文件:55.56 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS TRIPLE 3-INPUT AND GATE WITH 5 VOLT TOLERANT I/O 文件:55.56 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS TRIPLE 3-INPUT AND GATE WITH 5 VOLT TOLERANT I/O 文件:55.56 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS TRIPLE 3-INPUT AND GATE WITH 5 VOLT TOLERANT I/O 文件:55.56 Kbytes Page:5 Pages | IDT | |||
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O 文件:61.76 Kbytes Page:6 Pages | IDT | |||
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O 文件:61.76 Kbytes Page:6 Pages | IDT | |||
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O | RENESAS 瑞萨 | |||
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O 文件:61.76 Kbytes Page:6 Pages | IDT | |||
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O 文件:61.76 Kbytes Page:6 Pages | IDT | |||
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH 5 VOLT TOLERANT I/O 文件:87.91 Kbytes Page:6 Pages | IDT | |||
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH 5 VOLT TOLERANT I/O 文件:87.91 Kbytes Page:6 Pages | IDT | |||
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH 5 VOLT TOLERANT I/O 文件:87.91 Kbytes Page:6 Pages | IDT | |||
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH 5 VOLT TOLERANT I/O 文件:87.91 Kbytes Page:6 Pages | IDT |
IDT74LVC产品属性
- 类型
描述
- 型号
IDT74LVC
- 制造商
Integrated Device Technology Inc
- 功能描述
Flip Flop, Dual, J/K Type, 16 Pin, Plastic, SSOP
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
IDT |
24+ |
NA/ |
3449 |
原装现货,当天可交货,原型号开票 |
|||
IDT |
24+ |
TSSOP48 |
880000 |
明嘉莱只做原装正品现货 |
|||
IDT |
25+23+ |
TSSOP48 |
10322 |
绝对原装正品全新进口深圳现货 |
|||
IDT |
25+ |
TSSOP-48 |
4500 |
全新原装、诚信经营、公司现货销售 |
|||
IDT |
23+ |
TSSOP |
5700 |
绝对全新原装!现货!特价!请放心订购! |
|||
IDT |
25+ |
1132 |
全新原装!优势库存热卖中! |
||||
IDT |
新 |
166 |
全新原装 货期两周 |
||||
IDT |
24+ |
TSSOP48 |
54000 |
郑重承诺只做原装进口现货 |
|||
IDT |
25+ |
TSSOP |
86910 |
全新原装进口现货价格优惠 本公司承诺原装正品假一赔 |
|||
IDT |
25+ |
TSSOP48 |
548 |
全新原装正品支持含税 |
IDT74LVC规格书下载地址
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2019-12-2IDT74ALVC16835PF全新原装现货
可立即发货
2019-9-24
DdatasheetPDF页码索引
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