3.3V Synchronous ZBT SRAMs

文件：489.92 Kbytes Page：25 Pages

128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

Description The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Features

3.3V Synchronous ZBT SRAMs

文件：489.92 Kbytes Page：25 Pages

128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos

128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos