丝印代码：ICS87016AYLF；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

丝印代码：ICS87016AYLF；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

丝印代码：ICS87016AYLF；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

丝印代码：ICS87016AYLF；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

丝印代码：ICS87016AYIL；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

Features • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input • CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Max

丝印代码：ICS87016AYIL；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

Features • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input • CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Max

丝印代码：ICS87016AYLF；Low Skew LVCMOS/LVTTL Clock Generator

文件：271.26 Kbytes Page：17 Pages

丝印代码：ICS87016AYLF；Low Skew LVCMOS/LVTTL Clock Generator

文件：271.26 Kbytes Page：17 Pages

Low Skew LVCMOS/LVTTL Clock Generator

文件：271.26 Kbytes Page：17 Pages

Maximum output frequency

文件：383.65 Kbytes Page：17 Pages