Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

Low Skew,1-to-16 LVCMOS/LVTTL Clock Generator

The 87016 is a low skew, 1:16 LVCMOS/LVTTL Clock Generator. The device has 4 banks of 4 outputs and each bank can be independently selected for ÷1 or ÷2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2. • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)\n• Selectable differential CLK1, nCLK1 or LVCMOS clock input\n• CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\n• CLK0 supports the following input types: LVCMOS, LVTTL\n• Maximum output freq;

Low Skew LVCMOS/LVTTL Clock Generator

文件：271.26 Kbytes Page：17 Pages

丝印代码：ICS87016AYLF；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

丝印代码：ICS87016AYLF；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

丝印代码：ICS87016AYLF；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

丝印代码：ICS87016AYLF；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

Features • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input • CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Max

Low Skew,1-to-16 LVCMOS/LVTTL Clock Generator

The 87016I is a low skew, 1:16 LVCMOS/LVTTL Clock Generator and is a member of the HiPerClockS family of High Performance Clock Solutions. The device has 4 banks of 4 outputs and each bank can be independently selected for ÷1 or ÷2 frequency operation. Each bank also has its own power supply pins so • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)\n• CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\n• Maximum output frequency: 250MHz\n• Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operation\n• Output skew: 170ps (maxim;

封装/外壳：48-LQFP 包装：卷带（TR） 描述：IC CLK GENERATOR 1:6 48-LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：48-LQFP 包装：卷带（TR） 描述：IC CLK GENERATOR 1:6 48-LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

丝印代码：ICS87016AYLF；Low Skew LVCMOS/LVTTL Clock Generator

文件：271.26 Kbytes Page：17 Pages

丝印代码：ICS87016AYLF；Low Skew LVCMOS/LVTTL Clock Generator

文件：271.26 Kbytes Page：17 Pages

Maximum output frequency

文件：383.65 Kbytes Page：17 Pages

丝印代码：ICS87016AYIL；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

Features • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input • CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Max