0.5 dB LSB GaAs MMIC 6-BIT DIGITAL SERIAL CONTROL ATTENUATOR, DC - 4 GHz

文件：968.22 Kbytes Page：8 Pages

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL SERIAL CONTROL ATTENUATOR, DC - 4 GHz

文件：968.22 Kbytes Page：8 Pages

0.5dB LSB GaAs MMIC 6位数字串行控制衰减器，DC - 4 GHz

封装/外壳：24-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：RF ATTENUATOR 31.5DB 50OHM 24QFN RF/IF，射频/中频和 RFID 衰减器

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL SERIAL CONTROL ATTENUATOR, DC - 4 GHz

文件：742.8 Kbytes Page：9 Pages

封装/外壳：24-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：RF ATTENUATOR 31.5DB 50OHM 24QFN RF/IF，射频/中频和 RFID 衰减器

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL SERIAL CONTROL ATTENUATOR, DC - 3 GHz

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL SERIAL CONTROL ATTENUATOR, DC - 3.0 GHz

文件：469.72 Kbytes Page：8 Pages

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL SERIAL CONTROL ATTENUATOR, DC - 3 GHz

文件：322.62 Kbytes Page：8 Pages

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL SERIAL CONTROL ATTENUATOR, DC - 3 GHz

文件：322.62 Kbytes Page：8 Pages

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL SERIAL CONTROL ATTENUATOR, DC - 3 GHz

文件：621.7 Kbytes Page：8 Pages

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL SERIAL CONTROL ATTENUATOR, DC - 3.0 GHz

文件：469.72 Kbytes Page：8 Pages

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL SERIAL CONTROL ATTENUATOR, DC - 3 GHz

文件：322.62 Kbytes Page：8 Pages

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL SERIAL CONTROL ATTENUATOR, DC - 3.0 GHz

TREK 542A

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CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b