Parallel-Load 8-bit Shift Register

Features • Ordering Information

Parallel-Load 8-bit Shift Register

文件：96.23 Kbytes Page：8 Pages

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also featur

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also featur

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature