Octal Transparent Latches (with 3-state outputs)

Description When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns hig

Octal Transparent Latches (with 3-state outputs)

文件：161.18 Kbytes Page：13 Pages

Octal D-type transparent latch; 3-state; inverting

GENERAL DESCRIPTION The 74HC/HCT563 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no.7A. The 74HC/HCT563 are octal D-type transparent latches featuring separate D-type inputs for each latch

Octal D-type transparent latch 3-state inverting

GENERAL DESCRIPTION The 74HC/HCT563 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no.7A. The 74HC/HCT563 are octal D-type transparent latches featuring separate D-type inputs for each latch

High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：50.92 Kbytes Page：9 Pages

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：286.35 Kbytes Page：14 Pages

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：288.18 Kbytes Page：14 Pages