Programmable Frequency Divider/Digital Timer

Description This device divides the incoming clock frequency by a number (a power of 2) that is preset by the Programming inputs. It has two Clock inputs, either of which may be used as a clock inhibit. The device also has an active-low Reset, which initializes the internal flip-flop states. Test

Programmable Frequency Divider/Digital Timer

Description This device divides the incoming clock frequency by a number (a power of 2) that is preset by the Programming inputs. It has two Clock inputs, either of which may be used as a clock inhibit. The device also has an active-low Reset, which initializes the internal flip-flop states. Test

Programmable Frequency Divider/Digital Timer

Description This device divides the incoming clock frequency by a number (a power of 2) that is preset by the Programming inputs. It has two Clock inputs, either of which may be used as a clock inhibit. The device also has an active-low Reset, which initializes the internal flip-flop states. Test

PROGRAMMABLE DIVIDER/TIMER

DESCRIPTION The 54/74HC292/7292 and HC294/7294 are high speed CMOS PROGRAMMABLE DIVIDER/TIMER fabricated with silicon C2MOS technology. ■ HIGH SPEED fMAX = 70 MHz (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL =

PROGRAMMABLE DIVIDER/TIMER

DESCRIPTION The 54/74HC292/7292 and HC294/7294 are high speed CMOS PROGRAMMABLE DIVIDER/TIMER fabricated with silicon C2MOS technology. ■ HIGH SPEED fMAX = 70 MHz (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL =