4-bit Parallel-Access Shift Register

Description This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; shift from QA towards QD. Features • High Speed Operation: tpd (Clock to Q) = 13 n

4-bit parallel access shift register

GENERAL DESCRIPTION The 74HC/HCT195 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous master reset • J,K, (D) inputs to the first stage • Fully syn

High Speed CMOS Logic 4-Bit Parallel Access Register

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High-Speed CMOS Logic 4-Bit Parallel Access Register

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High-Speed CMOS Logic 4-Bit Parallel Access Register

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High-Speed CMOS Logic 4-Bit Parallel Access Register

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