4-bit D-type Register (with 3-state outputs)

Description The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. The input disable allows the

Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (

Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (

QUAD D-TYPE REGISTER 3-STATE

DESCRIPTION The M54/74HC173 is ahigh speedCMOSQUADDTYPE REGISTER (3-STATE) fabricated in silicon gate C2MOS technology. ■ HIGH SPEED fMAX = 73 MHz (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) at TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 VCC (MIN.)

High Speed CMOS Logic Quad D-Type Flip-Flop, Three-State

文件：57.51 Kbytes Page：10 Pages

High Speed CMOS Logic Quad D-Type Flip-Flop, Three-State

文件：57.51 Kbytes Page：10 Pages