Quad. Bus Buffer Gates (with 3-state outputs)

Description The HD74HC125, HD74HC126 require the 3-state control input C to be taken high to put the output into the high impedance condition, whereas the HD74HC125, HD74HC126 requiresthe control input to be low to put the output into high impedance. Features • High Speed Operation:

Quad. Bus Buffer Gates (with 3-state outputs)

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General-Purpose Logics-HD/RD74HC Series

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICCcategory: MSI

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICCcategory: MSI

Quad 3-State Noninverting Buffers

The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3–state memory address

Quad 3-State Noninverting Buffers

The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3–state memory address

Quad 3-State Noninverting Buffers

The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3–state memory address