Dual J-K Flip-Flops (with Preset and Clear)

Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Qoutputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logi

Dual J-K Flip-Flops (with Preset and Clear)

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Dual J-K Flip-Flops (with Preset and Clear)

Standard IC>General-Purpose Logics>HD74HC Series

Dual 4-bit Binary Counters

Dual J-K Flip-Flops (with Preset and Clear)

文件：102.89 Kbytes Page：7 Pages

Dual J-K Flip-Flops (with Preset and Clear)

文件：102.89 Kbytes Page：7 Pages

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

Dual JK flip-flop with set and reset; negative-edge trigger

1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate indepen

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Bus Drive Capability: 15 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS112.

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

High Speed CMOS Logic

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