Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)

Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Features • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V

Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)

Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Features • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V

Standard IC>General-Purpose Logics>HD74HC Series

Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)

Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Features • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V

Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)