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GAL16V8D-15价格
参考价格：￥16.8516
型号：GAL16V8D-15LJN 品牌：Lattice Semiconductor 备注：这里有GAL16V8D-15多少钱，2025年最近7天走势，今日出价，今日竞价，GAL16V8D-15批发/采购报价，GAL16V8D-15行情走势销售排行榜，GAL16V8D-15报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 |   | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：293.59 Kbytes Page：8 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
封装/外壳：20-LCC（J 形引线） 包装：管件 描述：IC CPLD 8MC 15NS 20PLCC 集成电路（IC） CPLD（复杂可编程逻辑器件） | ETC 知名厂家 | ETC | | |
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
IC CPLD 8MC 15NS 20PLCC | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic™ | Lattice 莱迪思 | | ||
封装/外壳：20-LCC（J 形引线） 包装：托盘 描述：IC CPLD 8MC 15NS 20PLCC 集成电路（IC） CPLD（复杂可编程逻辑器件） | ETC 知名厂家 | ETC | | |
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：293.59 Kbytes Page：8 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | |
GAL16V8D-15产品属性
- 类型
描述
- 型号
GAL16V8D-15
- 制造商
LATTICE
- 制造商全称
Lattice Semiconductor
- 功能描述
High Performance E2CMOS PLD Generic Array Logic
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
LATTICE/莱迪斯 |
24+ |
PLCC |
500 |
大批量供应优势库存热卖 |
|||
LATTICE/莱迪斯 |
21+ |
PLCC |
1062 |
只做原装正品,不止网上数量,欢迎电话微信查询! |
|||
Lattice Semiconductor Corporat |
21+ |
20-LCC(J 形引线) |
460 |
100%进口原装!长期供应!绝对优势价格(诚信经营 |
|||
Lattice |
23+ |
PLCC |
8560 |
受权代理!全新原装现货特价热卖! |
|||
LATTICE |
23+ |
PLCC20 |
6500 |
全新原装假一赔十 |
|||
LATTICE |
1015+ |
PLCC |
5300 |
进口原装特价热卖中,可开17票! |
|||
LATTICE/莱迪斯 |
2025+ |
PLCC-20 |
5000 |
原装进口价格优 请找坤融电子! |
|||
LATTICE/莱迪斯 |
24+ |
PLCC-20 |
9600 |
原装现货,优势供应,支持实单! |
|||
Lattice |
24+ |
PLCC |
20000 |
全新原厂原装，进口正品现货，正规渠道可含税！！ |
|||
Lattice(莱迪斯) |
24+ |
标准封装 |
11049 |
原厂渠道供应,大量现货,原型号开票。 |
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GAL16V8D-15数据表相关新闻
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開發板及套件 - ARM This new Dev Board version has the same build as the existing 1 GB Dev Board with 4 GB RAM built in.
2021-1-18GAL16V8D-15LJN
搜索： SMD/SMT SPLD - 简单可编程逻辑器件 , TSSOP-20 SPLD - 简单可编程逻辑器件 , TSSOP-20 SPLD - 简单可编程逻辑器件 , STQFN-12 SPLD - 简单可编程逻辑器件
2020-7-13GAL16V8D-15LD/883产品规格参数
GAL16V8D-15LD/883
2020-7-10GAL16V8D-15LD/883
SPLD - 简单可编程逻辑器件
2019-12-18
DdatasheetPDF页码索引
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