General Description

These dual N & P Channel logic level enhancement mode field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switching applications. Since bias resistors are not required this dual digital FET can replace several digital transistors with different bias resistors.

Features

■ N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 Ω @ VGS= 4.5 V

■ P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 Ω @ VGS= -4.5 V.

■ Very low level gate drive requirements allowing direct

operation in 3 V circuits. VGS(th) < 1.0V.

■ Gate-Source Zener for ESD ruggedness.

>6kV Human Body Model

■ Replace multiple dual NPN & PNP digital transistors.