3.3V LVDS 2-Bit High Speed Differential Receiver

General Description This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low pow

3.3V LVDS 2-Bit High Speed Differential Receiver

3.3V LVDS 2-Bit High Speed Differential Receiver

General Description This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low pow

封装/外壳：14-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC RECEIVER 0/2 14TSSOP 集成电路（IC） 驱动器，接收器，收发器

封装/外壳：14-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC RECEIVER 0/2 14TSSOP 集成电路（IC） 驱动器，接收器，收发器

Pulse Transformers

RoHS compliant UL 94V-0 package material Isolation to 4kVrms Compact footprint PCB mounting Backward compatible with Sn/Pb soldering systems

Heyco-Flex?줞ounting Brackets

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Heyco-Flex™Mounting Brackets

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20mm COIN CELL HOLDERS

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Pulse Transformers

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