SRAM-Based LUT Devices

The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store conf

Configuration Devices for SRAM-Based LUT Devices

[Altera Corporation] Functional Description With SRAM-based devices, configuration data must be reloaded each time the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based APEX II, APEX 20K, Mercury, ACEX, and FLEX dev

Configuration Devices for SRAM-Based LUT Devices

Functional Description With SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone,

Configuration Devices for SRAM-Based LUT Devices

Functional Description With SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone,

Configuration Devices for SRAM-Based LUT Devices

Functional Description With SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone,

Configuration Devices for SRAM-Based

文件：386.07 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based LUT Devices

Functional Description With SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone,

Configuration Devices for SRAM-Based LUT Devices

文件：397.95 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based

文件：386.07 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based LUT Devices

封装/外壳：20-LCC（J 形引线） 包装：托盘 描述：IC CONFIG DEVICE 440KBIT 20PLCC 集成电路（IC） 用于 FPGA 的配置 PROM

Configuration Devices for SRAM-Based

文件：386.07 Kbytes Page：26 Pages

封装/外壳：20-LCC（J 形引线） 包装：托盘 描述：IC CONFIG DEVICE 20PLCC 集成电路（IC） 用于 FPGA 的配置 PROM

Configuration Devices for SRAM-Based LUT Devices

文件：397.95 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based

文件：386.07 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based

文件：386.07 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based LUT Devices

文件：397.95 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based LUT Devices

文件：397.95 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based

文件：386.07 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based LUT Devices

文件：397.95 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based

文件：386.07 Kbytes Page：26 Pages

Enhanced Configuration (EPC) Devices Datasheet

文件：633.7 Kbytes Page：36 Pages

Configuration Devices for SRAM-Based

文件：386.07 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based LUT Devices

文件：397.95 Kbytes Page：26 Pages

Configuration Devices for SRAM-Based LUT Devices

D Series

FEATURES • Low losses • High stability • High capacitance in small size • Kinked (preferred) or straight leads • Compliant to RoHS directive 2002/95/EC APPLICATIONS • Bypassing • Coupling • Resonant circuit

Low-Voltage Full-Bridge Brushless DC Motor Driver with Hall Element Commutation

Description The A1441 is a full-bridge motor driver designed to drive low-voltage bipolar brushless dc motors. Commutation of the motor is achieved by use of a single Hall element sensor to detect the position of an alternating-pole ring magnet. A high density merged Bipolar-CMOS semiconductor pr

Low-Voltage Full-Bridge Brushless DC Motor Driver with Hall Element Commutation

Features and Benefits ▪ Single-chip solution for high reliability ▪ Chopper stabilization technique for precise signal response over operating range ▪ 2.0 to 4.0 V operation ▪ Sleep mode pin allowing external logic signal enable/ disable to reduce average power consumption ▪ Restart feature

Low-Voltage Full-Bridge Brushless DC Motor Driver with Hall Element Commutation

Features and Benefits ▪ Single-chip solution for high reliability ▪ Chopper stabilization technique for precise signal response over operating range ▪ 2.0 to 4.0 V operation ▪ Sleep mode pin allowing external logic signal enable/ disable to reduce average power consumption ▪ Restart feature

Medium Power, N or SMK Connectors

文件：536.45 Kbytes Page：1 Pages