Horizontal Genlock, 8 FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

Horizontal Genlock, 8FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

Horizontal Genlock, 8FSC

The EL4585 is a PLL (Phase Lock Loop) sub-system, designed for video applications and also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

Horizontal Genlock, 8FSC

丝印代码：EL4585CN；Horizontal Genlock, 8FSC

The EL4585 is a PLL (Phase Lock Loop) sub-system, designed for video applications and also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

丝印代码：EL4585CS；Horizontal Genlock, 8FSC

The EL4585 is a PLL (Phase Lock Loop) sub-system, designed for video applications and also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

丝印代码：EL4585CS；Horizontal Genlock, 8FSC

The EL4585 is a PLL (Phase Lock Loop) sub-system, designed for video applications and also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

丝印代码：EL4585CS；Horizontal Genlock, 8FSC

The EL4585 is a PLL (Phase Lock Loop) sub-system, designed for video applications and also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

丝印代码：EL4585CSZ；Horizontal Genlock, 8FSC

The EL4585 is a PLL (Phase Lock Loop) sub-system, designed for video applications and also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

丝印代码：EL4585CSZ；Horizontal Genlock, 8FSC

The EL4585 is a PLL (Phase Lock Loop) sub-system, designed for video applications and also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

丝印代码：EL4585CSZ；Horizontal Genlock, 8FSC

The EL4585 is a PLL (Phase Lock Loop) sub-system, designed for video applications and also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

Horizontal Genlock, 8 FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

Horizontal Genlock, 8FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

Horizontal Genlock, 8 FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

Horizontal Genlock, 8FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

Horizontal Genlock, 8 FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

Horizontal Genlock, 8FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

Horizontal Genlock, 8FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

Horizontal Genlock, 8FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

Horizontal Genlock, 8FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

Horizontal Genlock, 8FSC

General Description The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan ra

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC PLL VIDEO GP 36MHZ 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC GENLOCK HORZ 8FSC 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

4-BIT MAGNITUDE COMPARATOR

DESCRIPTION The HCC4585B (extended temperature range) and HCF4585B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package, and plastic micropackage. ■ EXPANSION TO 8, 12, 16 ... 4 N BITS BY CASCADING UNITS ■ ME

4-BIT MAGNITUDE COMPARATOR

DESCRIPTION The HCC4585B (extended temperature range) and HCF4585B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package, and plastic micropackage. ■ EXPANSION TO 8, 12, 16 ... 4 N BITS BY CASCADING UNITS ■ ME

4-bit magnitude comparator

DESCRIPTION The HEF4585B is a 4-bit magnitude comparator which compares two 4-bit words (A and B), whether they are ‘less than’, ‘equal to’, or ‘greater than’. Each word has four parallel inputs (A0 to A3 and B0 to B3); A3 and B3 being the most significant inputs. Three outputs are provided; A

4-bit magnitude comparator

DESCRIPTION The HEF4585B is a 4-bit magnitude comparator which compares two 4-bit words (A and B), whether they are ‘less than’, ‘equal to’, or ‘greater than’. Each word has four parallel inputs (A0 to A3 and B0 to B3); A3 and B3 being the most significant inputs. Three outputs are provided; A

4-bit magnitude comparator

DESCRIPTION The HEF4585B is a 4-bit magnitude comparator which compares two 4-bit words (A and B), whether they are ‘less than’, ‘equal to’, or ‘greater than’. Each word has four parallel inputs (A0 to A3 and B0 to B3); A3 and B3 being the most significant inputs. Three outputs are provided; A