DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：916.1 Kbytes Page：17 Pages

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR）剪切带（CT） 描述：IC TRANSCEIVER HALF 1/1 24TSSOP 集成电路（IC） 驱动器，接收器，收发器

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：165.48 Kbytes Page：11 Pages

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：580.99 Kbytes Page：12 Pages

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：919.63 Kbytes Page：17 Pages

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：916.1 Kbytes Page：17 Pages

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC TRANSCEIVER HALF 1/1 24TSSOP 集成电路（IC） 驱动器，接收器，收发器

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：919.63 Kbytes Page：17 Pages

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：916.1 Kbytes Page：17 Pages

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：919.63 Kbytes Page：17 Pages