DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：919.63 Kbytes Page：17 Pages

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：165.48 Kbytes Page：11 Pages

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：580.99 Kbytes Page：12 Pages

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：919.63 Kbytes Page：17 Pages

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：916.1 Kbytes Page：17 Pages

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •