DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

1FEATURES 2• Single +3.3V Supply • Chipset (Tx + Rx) Power Consumption

3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

文件：378.63 Kbytes Page：17 Pages

DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link??6 MHz, 3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link??6 MHz

文件：250.02 Kbytes Page：12 Pages

3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-66 MHz, 3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link-66 MHz

文件：378.71 Kbytes Page：14 Pages

3.3-V Rising Edge Data Strobe LVDS Receiver

文件：2.40138 Mbytes Page：34 Pages

3.3-V Rising Edge Data Strobe LVDS Receiver

文件：2.40138 Mbytes Page：34 Pages

封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC INTERFACE SPECIALIZED 56TSSOP 集成电路（IC） 专用

3.3-V Rising Edge Data Strobe LVDS Receiver

文件：2.40138 Mbytes Page：34 Pages

3.3-V Rising Edge Data Strobe LVDS Receiver

文件：2.40138 Mbytes Page：34 Pages

3.3-V Rising Edge Data Strobe LVDS Receiver

文件：2.40138 Mbytes Page：34 Pages

封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC INTERFACE SPECIALIZED 56TSSOP 集成电路（IC） 专用

3.3-V Rising Edge Data Strobe LVDS Receiver

文件：2.40138 Mbytes Page：34 Pages

3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-66 MHz, 3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link-66 MHz

文件：378.71 Kbytes Page：14 Pages

3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link??6 MHz, 3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link??6 MHz

文件：250.02 Kbytes Page：12 Pages

3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-66 MHz, 3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link-66 MHz

文件：312.6 Kbytes Page：13 Pages