DRV8701 Brushed DC Motor Full-Bridge Gate Driver

1 Features 1• Single H-Bridge Gate Driver – Drives Four External N-Channel MOSFETs – Supports 100% PWM Duty Cycle • 5.9-V to 45-V Operating Supply Voltage Range • Two Control Interface Options – PH/EN (DRV8701E) – PWM (DRV8701P) • Adjustable Gate Drive (5 Levels) – 6-mA to 150-mA Sour

封装/外壳：24-VFQFN 裸露焊盘 功能：控制器 - 电流管理 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC MOTOR DRIVER 0V-5.5V 24VQFN 集成电路（IC） 电机驱动器，控制器

DRV8701 Brushed DC Motor Full-Bridge Gate Driver

文件：1.76161 Mbytes Page：42 Pages

DRV8701 Brushed DC Motor Full-Bridge Gate Driver

1 Features 1• Single H-Bridge Gate Driver – Drives Four External N-Channel MOSFETs – Supports 100% PWM Duty Cycle • 5.9-V to 45-V Operating Supply Voltage Range • Two Control Interface Options – PH/EN (DRV8701E) – PWM (DRV8701P) • Adjustable Gate Drive (5 Levels) – 6-mA to 150-mA Sour

DRV8701 Brushed DC Motor Full-Bridge Gate Driver

1 Features 1• Single H-Bridge Gate Driver – Drives Four External N-Channel MOSFETs – Supports 100% PWM Duty Cycle • 5.9-V to 45-V Operating Supply Voltage Range • Two Control Interface Options – PH/EN (DRV8701E) – PWM (DRV8701P) • Adjustable Gate Drive (5 Levels) – 6-mA to 150-mA Sour

Low Skew, ÷1, ÷2 LVCMOS/LVTTL Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • One LVCMOS/LVTTL clock input • Maximum output frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Output skew: 250ps (maximum) • Part-to-part skew: 600ps (maximum) • Bank s

Mass Flow Meter for Gases (MFM)

The mass flow meter (MFM) type 8701 is suited for measuring the mass flow of gases over a big flow range. The thermal MEMS sensor is located directly in the gas stream and therefore reaches very fast response times. Type 8701 can optionally be calibrated for two different gases; the user can sw

Low Skew, ÷1, ÷2 Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • LVCMOS / LVTTL clock input • Maximum input frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Bank skew: 200ps • Output skew: 250ps • Multiple frequency skew: 300ps • Par

Low Skew, ÷1, ÷2 Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • LVCMOS / LVTTL clock input • Maximum input frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Bank skew: 200ps • Output skew: 250ps • Multiple frequency skew: 300ps • Par

CAPTIVE PANEL SCREWS

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