位置:首页 > IC中文资料第916页 > DM74LS13
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
DM74LS13 | DUAL 4-INPUT SCHMITT TRIGGER 文件:63.03 Kbytes Page:3 Pages | NSC 国半 | ||
DM74LS13 | DUAL 4-INPUT SCHMITT TRIGGER | TI 德州仪器 | ||
Quad 2-Input NAND Gate with Schmitt Trigger Input General Description This device contains four independent gates each of which performs the logic NAND function. Each input has hystere sis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. | FAIRCHILD 仙童半导体 | |||
Quad 2-Input NAND Gate with Schmitt Trigger Input General Description This device contains four independent gates each of which performs the logic NAND function. Each input has hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. | SYC | |||
Quad 2-Input NAND Gate with Schmitt Trigger Input General Description This device contains four independent gates each of which performs the logic NAND function. Each input has hystere sis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. | FAIRCHILD 仙童半导体 | |||
Quad 2-Input NAND Gate with Schmitt Trigger Input General Description This device contains four independent gates each of which performs the logic NAND function. Each input has hystere sis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. | FAIRCHILD 仙童半导体 | |||
Quad 2-Input NAND Gate with Schmitt Trigger Input General Description This device contains four independent gates each of which performs the logic NAND function. Each input has hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. | SYC | |||
Quad 2-Input NAND Gate with Schmitt Trigger Input General Description This device contains four independent gates each of which performs the logic NAND function. Each input has hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. | SYC | |||
Quad 2-Input NAND Gate with Schmitt Trigger Input General Description This device contains four independent gates each of which performs the logic NAND function. Each input has hystere sis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. | FAIRCHILD 仙童半导体 | |||
Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs General Description This device contains four independent gates, each of which performs the logic exclusive-OR function. | FAIRCHILD 仙童半导体 | |||
Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs General Description This device contains four independent gates, each of which performs the logic exclusive-OR function. | FAIRCHILD 仙童半导体 | |||
Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs General Description This device contains four independent gates, each of which performs the logic exclusive-OR function. | FAIRCHILD 仙童半导体 | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. Whe | FAIRCHILD 仙童半导体 | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. Whe | FAIRCHILD 仙童半导体 | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SOLIDSTATE | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SYC | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SYC | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SOLIDSTATE | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. Whe | FAIRCHILD 仙童半导体 | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SOLIDSTATE | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SYC | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. Whe | FAIRCHILD 仙童半导体 | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SYC | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SOLIDSTATE | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. Whe | FAIRCHILD 仙童半导体 | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. Whe | FAIRCHILD 仙童半导体 | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SOLIDSTATE | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SYC | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SOLIDSTATE | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. | SYC | |||
Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. Whe | FAIRCHILD 仙童半导体 | |||
13-INPUT NAND GATE 文件:52.39 Kbytes Page:2 Pages | NSC 国半 | |||
13-INPUT NAND GATE | TI 德州仪器 | |||
13-INPUT NAND GATE 文件:52.39 Kbytes Page:2 Pages | NSC 国半 | |||
13-INPUT NAND GATE 文件:52.39 Kbytes Page:2 Pages | NSC 国半 | |||
QUAD 2-INPUT EXCLUSIVE-OR GATE WITH OPEN-COLLECTOR OUTPUTS 文件:52.67 Kbytes Page:2 Pages | NSC 国半 | |||
Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs 文件:91.35 Kbytes Page:4 Pages | NSC 国半 | |||
Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs | ONSEMI 安森美半导体 | |||
QUAD 2-INPUT EXCLUSIVE-OR GATE WITH OPEN-COLLECTOR OUTPUTS 文件:52.67 Kbytes Page:2 Pages | NSC 国半 | |||
QUAD 2-INPUT EXCLUSIVE-OR GATE WITH OPEN-COLLECTOR OUTPUTS 文件:52.67 Kbytes Page:2 Pages | NSC 国半 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
封装/外壳:16-SOIC(0.154",3.90mm 宽) 包装:管件 描述:IC DECODER/DEMUX 1X3:8 16SOIC 集成电路(IC) 信号开关,多路复用器,解码器 | ONSEMI 安森美半导体 | |||
封装/外壳:16-DIP(0.300",7.62mm) 包装:管件 描述:IC DECODER/DEMUX 1X3:8 16DIP 集成电路(IC) 信号开关,多路复用器,解码器 | ONSEMI 安森美半导体 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
Decoders/Demultiplexers 文件:165.29 Kbytes Page:8 Pages | NSC 国半 | |||
DUAL 4-INPUT SCHMITT TRIGGER 文件:63.03 Kbytes Page:3 Pages | NSC 国半 | |||
DUAL 4-INPUT SCHMITT TRIGGER 文件:63.03 Kbytes Page:3 Pages | NSC 国半 | |||
SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS/74LS13 and SN54LS/74LS14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise m | MOTOROLA 摩托罗拉 | |||
Dual 4-input Positive NAND Schmitt Triggers ● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....) | HITACHIHitachi Semiconductor 日立日立公司 |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
QUAD 2-INPUT SCHMITT TRIGGER NAND GATE | MOTOROLA 摩托罗拉 | MOTOROLA | ||
LOW POWER SCHOTTKY | ONSEMI 安森美半导体 | ONSEMI | ||
QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT TRIGGERS | TI 德州仪器 | TI | ||
Quad 2-Input NAND Gate with Schmitt Trigger Input | FAIRCHILD 仙童半导体 | FAIRCHILD | ||
Quadruple 2-input Positive NAND Schmitt-triggers | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | ||
QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT TRIGGERS | TI 德州仪器 | TI | ||
QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT TRIGGERS | TI 德州仪器 | TI | ||
LOW POWER SCHOTTKY | ONSEMI 安森美半导体 | ONSEMI | ||
QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT TRIGGERS | TI 德州仪器 | TI | ||
QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT TRIGGERS | TI 德州仪器 | TI | ||
LOW POWER SCHOTTKY | ONSEMI 安森美半导体 | ONSEMI | ||
QUAD 2-INPUT SCHMITT TRIGGER NAND GATE | MOTOROLA 摩托罗拉 | MOTOROLA | ||
QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT TRIGGERS | TI 德州仪器 | TI |
DM74LS13产品属性
- 类型
描述
- 型号
DM74LS13
- 制造商
Texas Instruments
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
FAIRCHILD/仙童 |
25+ |
SOP |
154683 |
明嘉莱只做原装正品现货 |
|||
NS/国半 |
22+ |
SOP |
12245 |
现货,原厂原装假一罚十! |
|||
NS |
24+ |
SOP3.9MM |
1738 |
只做原装正品现货 欢迎来电查询15919825718 |
|||
Fairchild/ON |
22+ |
16PDIP |
9000 |
原厂渠道,现货配单 |
|||
NATIONAL |
26+ |
原厂封装 |
39215 |
代理全系列销售,全新原装正品,价格优势,长期供应,量大可订 |
|||
原厂 |
23+ |
SOP-14 |
5000 |
原装正品,假一罚十 |
|||
FAIRCHILD/仙童 |
23+ |
PDIP-14 |
5000 |
只有原装,欢迎来电咨询! |
|||
FAIRCHILD |
25+ |
SOP16 |
3200 |
全新原装、诚信经营、公司现货销售 |
|||
NATIONAL |
23+ |
SOIC |
65480 |
||||
FAIRCHILD/仙童 |
2223+ |
SOP |
26800 |
只做原装正品假一赔十为客户做到零风险 |
DM74LS13规格书下载地址
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2020-7-10DM74LS241WM,DM74LS241WMX,DM74LS243N,DM74LS244N,DM74LS244SJX,DM74LS245N,DM74LS245SJX,DM74LS251M,DM74LS251MX,DM74LS251N,DM74LS253MX,DM74LS257BMX,DM74LS221MX,DM74LS221SJ,DM74LS221
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2019-12-8DM74ALS04BM-六反相器
DM74ALS04BM-六反相器,此装置包含6个独立的门,其中每个执行反向功能的逻辑。 特点 开关规格为50 pF 在整个温度开关规格保证和VCC范围 高级氧化隔离,离子注入肖特基TTL过程 功能和引脚对引脚兼容与肖特基和低功耗肖特基TTL对口 改进的AC性能超过肖特基二极管和低功耗肖特基同行 DM74ALS04BM:M14A 14引脚小外形集成电路(SOIC),JEDEC MS- 012,0.150窄 DM74ALS04BSJ: M14D 14引脚小外形封装(SOP),
2012-11-9
DdatasheetPDF页码索引
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