3 to 8 Line Decoder/Demultiplexer

General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. Whe

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC DECODER/DEMUX 1X3:8 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

3 to 8 Line Decoder/Demultiplexer

General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. Whe

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC DECODER/DEMUX 1X3:8 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

1-of-8 decoder/demultiplexer

DESCRIPTION The 74ALS138 decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled, provides eight mutually exclusive, active-Low outputs (Q0 – Q7). The device features three Enable inputs; two active-Low (E0, E1) and one active-High (E2). Every output will be High unless E0 and

1-of-8 decoder/demultiplexer

DESCRIPTION The 74ALS138 decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled, provides eight mutually exclusive, active-Low outputs (Q0 – Q7). The device features three Enable inputs; two active-Low (E0, E1) and one active-High (E2). Every output will be High unless E0 and

1-of-8 decoder/demultiplexer

DESCRIPTION The 74ALS138 decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled, provides eight mutually exclusive, active-Low outputs (Q0 – Q7). The device features three Enable inputs; two active-Low (E0, E1) and one active-High (E2). Every output will be High unless E0 and