Hex Inverters with Schmitt Trigger Inputs

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Hex Inverters with Schmitt Trigger Inputs

Quad 2-Input NAND Gates

General Description This device contains four independent gates each of which performs the logic NAND function.

Quad 2-Input NAND Gates

General Description This device contains four independent gates each of which performs the logic NAND function.

Quad 2-Input NAND Gates

General Description This device contains four independent gates each of which performs the logic NAND function.

Quad 2-Input NOR Gates

General Description This device contains four independent gates each of which performs the logic NOR function.

Quad 2-Input NOR Gates

General Description This device contains four independent gates each of which performs the logic NOR function.

Quad 2-Input NAND Gates with Open-Collector Outputs

General Description This device contains four independent gates each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

Quad 2-Input NAND Gates with Open-Collector Outputs

General Description This device contains four independent gates each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

Hex Inverting Gates

General Description This device contains six independent gates each of which performs the logic INVERT function.

Hex Inverting Gates

General Description This device contains six independent gates each of which performs the logic INVERT function.

Hex Inverting Gates

General Description This device contains six independent gates each of which performs the logic INVERT function.

Hex Inverters with Open-Collector Outputs

General Description This device contains six independent gates each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.

Hex Inverters with Open-Collector Outputs

General Description This device contains six independent gates each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.

Hex Inverting Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent buffers each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.

Hex Inverting Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent buffers each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.

Hex Inverting Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent buffers each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.

Hex Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent gates each of which performs a buffer function. The open-collector outputs require external pull-up resistors for proper logical operation.

Hex Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent gates each of which performs a buffer function. The open-collector outputs require external pull-up resistors for proper logical operation.

Hex Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent gates each of which performs a buffer function. The open-collector outputs require external pull-up resistors for proper logical operation.

Quad 2-Input AND Gates

General Description This device contains four independent gates each of which performs the logic AND function.

Quad 2-Input AND Gates

General Description This device contains four independent gates each of which performs the logic AND function.

One-Shot with Clear and Complementary Outputs

General Description The DM74121 is a monostable multivibrator featuring both positive and negative edge triggering with complementary outputs. An internal 2kΩtiming resistor is provided for design convenience minimizing component count and layout problems. this device can be used with a single ex

One-Shot with Clear and Complementary Outputs

General Description The DM74121 is a monostable multivibrator featuring both positive and negative edge triggering with complementary outputs. An internal 2kΩtiming resistor is provided for design convenience minimizing component count and layout problems. this device can be used with a single ex

Dual Retriggerable One-Shot with Clear and Complementary Outputs

General Description The DM74123 is a dual retriggerable monostable multivibrator capable of generating output pulses from a few nano-seconds to extremely long duration up to 100 duty cycle. Each device has three inputs permitting the choice of either leading-edge or trailing edge triggering.

Dual Retriggerable One-Shot with Clear and Complementary Outputs

General Description The DM74123 is a dual retriggerable monostable multivibrator capable of generating output pulses from a few nano-seconds to extremely long duration up to 100 duty cycle. Each device has three inputs permitting the choice of either leading-edge or trailing edge triggering.

Hex Inverter with Schmitt Trigger Input

General Description This device contains six independent gates each of which performs the logic INVERT function. Each input has hyster esis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output.

BCD to Decimal Decoders/Drivers

General Description These BCD-to-decimal decoders/drivers consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of BCD input logic ensures that all outputs remain OFF for all

BCD to Decimal Decoders/Drivers

General Description These BCD-to-decimal decoders/drivers consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of BCD input logic ensures that all outputs remain OFF for all

Hex Inverter with Schmitt Trigger Input

General Description This device contains six independent gates each of which performs the logic INVERT function. Each input has hyster esis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output.

Data Selectors/Multiplexers

General Description These data selectors/multiplexers contain full on-chip decoding to select the desired data source. The DM74150 selects one-of-sixteen data sources. The DM74150 has a strobe input which must be at a LOW logic level to enable these devices. A HIGH level at the strobe forces th

Data Selectors/Multiplexers

General Description These data selectors/multiplexers contain full on-chip decoding to select the desired data source. The DM74150 selects one-of-sixteen data sources. The DM74150 has a strobe input which must be at a LOW logic level to enable these devices. A HIGH level at the strobe forces th

Quad 2-Line to 1-Line Data Selectors/Multiplexer

General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. Features ■Buffered

Quad 2-Line to 1-Line Data Selectors/Multiplexer

General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. Features ■Buffered

Hex Inverting Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent gates each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.

8-Bit Serial In/Parallel Out Shift Registers

General Description These 8-bit shift registers feature gated serial inputs and n asynchronous clear. A LOW logic level at either serial input inhibits entry of the new data, and resets the first flip-flop to the LOW level at the next clock pulse, thus providing complete control over incoming d

8-Bit Parallel-to-Serial Converter

General Description The ’165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputting occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new da

8-Bit Parallel-to-Serial Converter

General Description The ’165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputting occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new da

Hex Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent gates each of which performs a buffer function. The open-collector outputs require external pull-up resistors for proper logical operation.

Hex/Quad D-Type Flip-Flop with Clear

Hex/Quad D Flip-Flops with Clear

Hex/Quad D Flip-Flops with Clear

Hex Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent gates each of which performs a buffer function. The open-collector outputs require external pull-up resistors for proper logical operation.

Hex Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent gates each of which performs a buffer function. The open-collector outputs require external pull-up resistors for proper logical operation.

Dual 4-Input NAND Gate

General Description This device contains two independent gates each of which performs the logic NAND function.

Dual 4-Input NAND Gate

General Description This device contains two independent gates each of which performs the logic NAND function.

Quad 2-Input NAND Gates with High Voltage Open-Collector Outputs

General Description This device contains four independent gates each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

Quad 2-Input NAND Gates with High Voltage Open-Collector Outputs

General Description This device contains four independent gates each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

Quad 2-Input NAND Buffers with Open-Collector Outputs

General Description This device contains four independent gates each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

Quad 2-Input NAND Buffers with Open-Collector Outputs

General Description This device contains four independent gates each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

Quad 2-Input NAND Buffers with Open-Collector Outputs

General Description This device contains four independent gates each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

BCD to Decimal Decoder

General Description These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of input logic ensures that all outputs remain off for all invalid (10–1

BCD to Decimal Decoder

General Description These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of input logic ensures that all outputs remain off for all invalid (10–1

BCD to Decimal Decoder

General Description These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of input logic ensures that all outputs remain off for all invalid (10–1

BCD to Decimal Decoders/Drivers

General Description These BCD-to-decimal decoders/drivers consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of BCD input logic ensures that all outputs remain OFF for all

BCD to 7-Segment Decoders/Drivers

General Description The DM7446A and DM7447A feature active-LOW outputs designed for driving common-anode LEDs or incandescent indicators directly. All of the circuits have full ripple-blanking input/output controls and a lamp test input. Segment identification and resultant displays are shown on

BCD to 7-Segment Decoders/Drivers

General Description The DM7446A and DM7447A feature active-LOW outputs designed for driving common-anode LEDs or incandescent indicators directly. All of the circuits have full ripple-blanking input/output controls and a lamp test input. Segment identification and resultant displays are shown on

BCD to 7-Segment Decoders/Drivers

General Description The DM7446A and DM7447A feature active-LOW outputs designed for driving common-anode LEDs or incandescent indicators directly. All of the circuits have full ripple-blanking input/output controls and a lamp test input. Segment identification and resultant displays are shown on

BCD to 7-Segment Decoders/Drivers

General Description The DM7446A and DM7447A feature active-LOW outputs designed for driving common-anode LEDs or incandescent indicators directly. All of the circuits have full ripple-blanking input/output controls and a lamp test input. Segment identification and resultant displays are shown on

Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of

Quad 2-Input NAND Gate

QUAD 2-INPUT NAND GATE

3/4 DIAMETER WIRE-WOUND, MULTI-TURN

Quad 2-Input NAND Gate

Quad 2-Input NAND Gate

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATE

TTL HD74/HD74S Series

Single Supply Quad Comparators

TRANSISTOR TRANSISTOR LOGIC

Quadruple 2input positive-nand gates

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

QUADRUPLE 2-INPUT POSITIVE-NAND GATES