Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of

Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of

封装/外壳：14-DIP（0.300"，7.62mm） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 14DIP 集成电路（IC） 触发器

QUAD BTL DRIVER WITH VOLTAGE REGULATOR

DESCRIPTION This device is a quad power driver circuit in BTL configuration, intended for use as a power driver for servo systems with a single supply. It’s specially dedicated to compact disc players and it’s capable of driving focus & tracking actuators sledge & spindle motors. The re

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages

Transistor transistor logic

INTEGRATED CIRCUIT PINOUTS

DUAL J-K FLIP-FLOPS WITH CLEAR

DUAL J-K FLIP-FLOPS WITH CLEAR