16K x 4 Static RAM

Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Features • High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 110 mW •

16K x 4 Static RAM

文件：266.19 Kbytes Page：9 Pages

16K x 4 Static RAM

Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Features • High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 110 mW •

16K x 4 Static RAM

Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Features • High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 110 mW •

16K x 4 Static RAM

Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Features • High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 110 mW •

16K x 4 Static RAM

Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Features • High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 110 mW •

16K x 4 Static RAM

Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Features • High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 110 mW •

16K x 4 Static RAM

Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Features • High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 110 mW •

16K x 4 Static RAM

Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Features • High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 110 mW •

16K x 4 Static RAM

Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Features • High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 110 mW •

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

Functional Description The CY7C1663KV18, and CY7C1665KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

Functional Description The CY7C1663KV18, and CY7C1665KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

Functional Description The CY7C1663KV18, and CY7C1665KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

Functional Description The CY7C1663KV18, and CY7C1665KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has

16K x 4 Static RAM

文件：266.19 Kbytes Page：9 Pages

16K x 4 Static RAM

文件：266.19 Kbytes Page：9 Pages

封装/外壳：165-LBGA 包装：托盘 描述：IC SRAM 144MBIT PARALLEL 165FBGA 集成电路（IC） 存储器

封装/外壳：165-LBGA 包装：托盘 描述：IC SRAM 144MBIT PARALLEL 165FBGA 集成电路（IC） 存储器

同步 SRAM

144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

文件：771.58 Kbytes Page：30 Pages

144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

文件：771.58 Kbytes Page：30 Pages

双倍数据速率 (DDR) 同步 SRAM

144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

文件：771.58 Kbytes Page：30 Pages