Functional Description

The CY7C1663KV18, and CY7C1665KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 550-MHz clock for high bandwidth

■ Four-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz

■ Available in 2.5-clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Quad data rate (QDR®) II+ operates with 2.5-cycle read latency when DOFF is asserted high

■ Operates similar to QDR I device with one cycle read latency when DOFF is asserted low

■ Available in × 18, and × 36 configurations

■ Full data coherency, providing most current data

■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD [1]

❐ Supports both 1.5-V and 1.8-V I/O supply

■ High-speed transceiver logic (HSTL) inputs and variable drive HSTL output buffers

■ Available in 165-ball fine-pitch ball grid array (FBGA) package (15 × 17 × 1.4 mm)

■ Offered in Pb-free package

■ JTAG 1149.1 compatible test access port

■ Phase locked loop (PLL) for accurate data placement