144-Mbit DDR II SRAM Two-Word Burst Architecture

Functional Description The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate ris

144-Mbit DDR II SRAM Two-Word Burst Architecture

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封装/外壳：165-LBGA 包装：托盘 描述：IC SRAM 144MBIT PARALLEL 165FBGA 集成电路（IC） 存储器

DDR-II CIO