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CY7C148价格
参考价格：￥831.0149
型号：CY7C1480BV25-167AXC 品牌：Cynergy 3 备注：这里有CY7C148多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C148批发/采购报价，CY7C148行情走势销售排行榜，CY7C148报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
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CY7C148 | 1K x 4 Static RAM Functional Description The CY7C148 and CY7C149 are high-performance CMOS static RAMs organized as 1024 by 4 bits. Easy memory expansion is provided by an active LOW chip select (CS) input and three-state outputs. The CY7C148 remains in a low-power mode as long as the device remains unselected; i. | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C148 | 1Kx4 Static RAM 文件：224.18 Kbytes Page：9 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | |
CY7C148 | 1Kx4 Static RAM | Infineon 英飞凌 | | |
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O operation ■ Fast clock-to-output times ❐ 3.0 ns (for 250 MHz device) ■ P | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-trigg | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-trigg | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-trigg | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-trigg | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-trigg | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-trigg | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-trigg | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-trigg | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-trigg | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-trigg | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip count | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip count | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip count | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip count | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip count | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip count | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip count | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip count | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip count | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C148产品属性
- 类型
描述
- 型号
CY7C148
- 制造商
Cypress Semiconductor
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYPRESS |
21+ |
QFP |
1398 |
只做原装正品,不止网上数量,欢迎电话微信查询! |
|||
CYPRESS |
2025+ |
N/A |
2000 |
原装原厂发货7-15工作日 |
|||
CYPRESS |
24+ |
BGA |
8500 |
只做原装正品假一赔十为客户做到零风险!! |
|||
Cypress |
23+ |
TQFP |
20000 |
||||
CYPRESS |
ROHS+Original |
NA |
1221 |
专业电子元器件供应链/QQ 350053121 /正纳电子 |
|||
CYPRESS/赛普拉斯 |
20+ |
FBGA-165 |
1050 |
||||
CYPRESS |
24+ |
DIP |
39500 |
进口原装现货 支持实单价优 |
|||
CYPRESS/赛普拉斯 |
20+ |
FBGA-165 |
1 |
进口原装现货假一赔万力挺实单 |
|||
CYPRESS |
24+ |
DIP |
30617 |
主打CYPRESS品牌价格绝对优势 |
|||
Cypress |
24+ |
TQFP |
8000 |
新到现货，只做全新原装正品 |
CY7C148规格书下载地址
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CY7C148数据表相关新闻
CY7C15632KV18-500BZXI
进口代理
2024-11-25CY7C1565KV18-500BZXI
进口代理
2023-10-24CY7C1462AV33-167AXC 原装现货
CY7C1462AV33-167AXC 可做含税，支持实单
2021-9-18CY7C1399B-12ZC 十年IC，一家专业军工级IC供货商
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2020-6-28
DdatasheetPDF页码索引
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