36-Mbit QDR짰 II SRAM 2-Word Burst Architecture

Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

36-Mbit QDR짰 II SRAM 2-Word Burst Architecture

Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

36-Mbit QDR짰 II SRAM Two-Word Burst Architecture

文件：895.24 Kbytes Page：33 Pages

36-Mbit QDR짰 II SRAM Two-Word Burst Architecture

文件：895.24 Kbytes Page：33 Pages

36-Mbit QDR짰 II SRAM Two-Word Burst Architecture

文件：895.24 Kbytes Page：33 Pages