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CY7C141价格
参考价格：￥326.4302
型号：CY7C1412AV18-200BZXC 品牌：Cynergy 3 备注：这里有CY7C141多少钱，2026年最近7天走势，今日出价，今日竞价，CY7C141批发/采购报价，CY7C141行情走势销售排行榜，CY7C141报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C141 | 1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C141 | 1K x 8 Dual-Port Static RAM 文件：570.93 Kbytes Page：19 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | |
36-Mbit QDR짰 II SRAM 2-Word Burst Architecture Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR짰 II SRAM 2-Word Burst Architecture Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR짰 II SRAM 2-Word Burst Architecture Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR짰 II SRAM 2-Word Burst Architecture Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR짰 II SRAM 2-Word Burst Architecture Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR짰 II SRAM 2-Word Burst Architecture Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR짰 II SRAM 2-Word Burst Architecture Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR짰 II SRAM 2-Word Burst Architecture Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR짰 II SRAM 2-Word Burst Architecture Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR짰 II SRAM 2-Word Burst Architecture Functional Description The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR짰 II SRAM 2-Word Burst Architecture 文件：894.7 Kbytes Page：31 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：277.14 Kbytes Page：23 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：277.14 Kbytes Page：23 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：277.14 Kbytes Page：23 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：277.14 Kbytes Page：23 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II??SRAM 2-Word Burst Architecture 文件：1.16885 Mbytes Page：25 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
36-Mbit QDR-II SRAM 2-Word Burst Architecture 文件：675.71 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C141产品属性
- 类型
描述
- 型号
CY7C141
- 功能描述
静态随机存取存储器 1Mx36 QDR II Burst 4 静态随机存取存储器
- RoHS
否
- 制造商
Cypress Semiconductor
- 存储容量
16 Mbit
- 组织
1 M x 16
- 访问时间
55 ns
- 电源电压-最大
3.6 V
- 电源电压-最小
2.2 V
- 最大工作电流
22 uA
- 最大工作温度
+ 85 C
- 最小工作温度
- 40 C
- 安装风格
SMD/SMT
- 封装/箱体
TSOP-48
- 封装
Tray
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYPRESS/赛普拉斯 |
25+ |
BGA |
32360 |
CYPRESS/赛普拉斯全新特价CY7C1418KV18-300BZXC即刻询购立享优惠#长期有货 |
|||
CYPRESS |
24+ |
BGA165 |
7850 |
只做原装正品现货或订货假一赔十! |
|||
CYPRESS |
24+ |
BGA |
8000 |
只做原装正品现货 |
|||
CYPRESS |
2023+ |
BGA |
53500 |
正品,原装现货 |
|||
CYPRESS/赛普拉斯 |
2025+ |
PLCC |
4495 |
原装进口价格优 请找坤融电子! |
|||
Cypress Semiconductor Corp |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
CYPRESS/赛普拉斯 |
25+ |
BGA |
12500 |
全新原装现货,假一赔十 |
|||
CYPRESS |
24+ |
BGA |
9860 |
全新原装现货/假一罚百! |
|||
CYPRESS |
17+ |
BGA |
6200 |
100%原装正品现货 |
|||
CY |
2021+ |
BGA |
9450 |
原装现货。 |
CY7C141规格书下载地址
CY7C141参数引脚图相关
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CY7C141数据表相关新闻
CY7C15632KV18-500BZXI
进口代理
2024-11-25CY7C1565KV18-500BZXI
进口代理
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