CY7C1383价格

参考价格:¥146.3304

型号:CY7C1383D-133AXC 品牌:Cynergy 3 备注:这里有CY7C1383多少钱,2025年最近7天走势,今日出价,今日竞价,CY7C1383批发/采购报价,CY7C1383行情走势销售排行榜,CY7C1383报价。
型号 功能描述 生产厂家 企业 LOGO 操作

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

512 횞 36/1M 횞 18 Flow-Thru SRAM

文件:599.35 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

文件:564.61 Kbytes Page:36 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件:501.06 Kbytes Page:35 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Infineon

英飞凌

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件:501.06 Kbytes Page:35 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件:501.06 Kbytes Page:35 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件:501.06 Kbytes Page:35 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件:501.06 Kbytes Page:35 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件:501.06 Kbytes Page:35 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件:501.06 Kbytes Page:35 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件:501.06 Kbytes Page:35 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件:501.06 Kbytes Page:35 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件:501.06 Kbytes Page:35 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件:501.06 Kbytes Page:35 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1383产品属性

  • 类型

    描述

  • 型号

    CY7C1383

  • 制造商

    Cypress Semiconductor

更新时间:2025-12-20 23:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
CYPRESS(赛普拉斯)
24+
LQFP100
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
CYPRESS/赛普拉斯
25+
BGA-165
996880
只做原装,欢迎来电资询
CYPRESS/赛普拉斯
23+
BGA-165
3000
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、
Cypress
25+
25000
原厂原包 深圳现货 主打品牌 假一赔百 可开票!
Cypress Semiconductor Corp
21+
168-TBGA
5280
进口原装!长期供应!绝对优势价格(诚信经营
Cypress
TQFP
3200
Cypress一级分销,原装原盒原包装!
Cypress Semiconductor Corp
23+
165-FBGA13x15
7300
专注配单,只做原装进口现货
CYPRESS/赛普拉斯
23+
BGA-165
98900
原厂原装正品现货!!
Cypress
22+
165FBGA (13x15)
9000
原厂渠道,现货配单
最新
2000
原装正品现货

CY7C1383数据表相关新闻