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CY7C1363价格

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型号：CY7C1363C-133AJXC 品牌：Cynergy 3 备注：这里有CY7C1363多少钱，2026年最近7天走势，今日出价，今日竞价，CY7C1363批发/采购报价，CY7C1363行情走势销售排行榜，CY7C1363报价。

型号	功能描述	生产厂家企业	LOGO
CY7C1363A	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-100AC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-100AI	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-100AJC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-100AJI	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-100BGC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-100BGI	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-117AC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-117AI	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-117AJC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-117AJI	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-117BGC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-117BGI	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-133AC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-133AI	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-133AJC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-133AJI	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-133BGC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-133BGI	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-150AC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-150AJC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363A-150BGC	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 6.0, 6.5	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-100AC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-100AI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-100AJC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-100AJI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-100BGC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-100BGI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-117AC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-117AI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-117AJC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-117AJI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-117BGC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-117BGI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-117BZC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-117BZI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-133AC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-133AI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-133AJC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-133AJI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-133BGC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-133BGI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-133BZC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363B-133BZI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counte	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-100AJXC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-100AJXI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-100AXC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-100AXI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-100BGC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-100BGI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-117AJXC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-117AJXI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-117AXC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-117AXI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-117BGC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-117BGI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-117BZC	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS
CY7C1363C-117BZI	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter	CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	CYPRESS

CY7C1363产品属性

类型
描述
型号
CY7C1363
制造商
CYPRESS
功能描述
*

CY7C1363供应商更多...

更新时间：2026-3-14 20:00:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市科芯源微电子有限公司	CY7C1363B-117BGC	CYPRESS/赛普拉斯	2026+		65248	百分百原装现货实单必成	询价
深圳市华斯顿科技有限公司	CY7C1363B-117BGC	CYPRESS	25+23+	BGA	24144	绝对原装正品全新进口深圳现货	询价
深圳市一线半导体有限公司	CY7C1363B-133AC	CYPRESS	24+	QFP	78		询价
深圳市毅创腾电子科技有限公司	CY7C1363B-117AJC	Cypress		QFP100	6200	Cypress一级分销,原装原盒原包装!	询价
标准国际(香港)有限公司	CY7C1363B-133AC	CY7C1363B-133AC	25+	23	23		询价
深圳市宏世佳电子科技有限公司	CY7C1363B-133AC	CYPRESS	2025+	TQFP	3625	全新原厂原装产品、公司现货销售	询价
深圳诚思涵科技有限公司	CY7C1363B-133AC	CYPRESS/赛普拉斯	24+	QFP	28131	只做原装公司现货库存	询价
深圳市科恒伟业电子有限公司	CY7C1363B-117AJC	CYPRESS/赛普拉斯	2450+	TQFP	6540	只做原厂原装正品现货或订货!终端工厂可以申请样品!	询价
深圳市华康联电子科技有限公司	CY7C1363B-133AC	CYPRESS/赛普拉斯	23+	QFP	98900	原厂原装正品现货!!	询价
深圳市蓝山航业科技有限公司	CY7C1363B-133AC	CYPRESS	25+		500000	行业低价,代理渠道	询价

CY7C1363芯片相关品牌

CY7C1363规格书下载地址

CY7C1363参数引脚图相关

CY7C1363数据表相关新闻

CY7C1329H-133AXC
CY7C1329H-133AXC
2023-8-7
CY7C1399B-12ZC 十年IC，一家专业军工级IC供货商
CY7C1399B-12ZC CY7C1399B-12ZC，ALTERA（阿尔特拉），军工级IC专业优势渠道
2020-7-16
CY7C1399B-12ZC十年IC，一家专业军工级IC供货商
CY7C1399B-12ZC十年IC，一家专业军工级IC供货商
2020-7-15
CY7C1370D-167AXI产品资料 CYPRESS/赛普拉斯
CY7C1370D-167AXI产品资料
2020-6-28
CY7C1350G-133AXC公司原装现货/长期供应
全新原装
2019-3-30
CY7C1354C-166AXI公司原装现货/长期供应
全新原装
2019-3-30

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CY7C1363价格

CY7C1363产品属性

CY7C1363供应商更多...

CY7C1363芯片相关品牌

CY7C1363规格书下载地址

CY7C1363参数引脚图相关

CY7C1363数据表相关新闻

CY7C1329H-133AXC

CY7C1399B-12ZC 十年IC，一家专业军工级IC供货商

CY7C1399B-12ZC十年IC，一家专业军工级IC供货商

CY7C1370D-167AXI产品资料 CYPRESS/赛普拉斯

CY7C1350G-133AXC公司原装现货/长期供应

CY7C1354C-166AXI公司原装现货/长期供应

DdatasheetPDF页码索引