CY7C1357价格

参考价格:¥69.8386

型号:CY7C1357C-100BZC 品牌:Cynergy 3 备注:这里有CY7C1357多少钱,2026年最近7天走势,今日出价,今日竞价,CY7C1357批发/采购报价,CY7C1357行情走势销售排行榜,CY7C1357报价。
型号 功能描述 生产厂家 企业 LOGO 操作

256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture

Functional Description The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells,

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture

Functional Description The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells,

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture

Functional Description The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells,

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture

Functional Description The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells,

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No B

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

Functional Description[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bu

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

IC SRAM 9M PARALLEL 100TQFP

INFINEON

英飞凌

封装/外壳:100-LQFP 包装:托盘托盘 描述:IC SRAM 9MBIT PARALLEL 100TQFP 集成电路(IC) 存储器

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256 K x 36 / 512 K x 18) Flow-through SRAM with NoBL Architecture

文件:795.58 Kbytes Page:32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256 K 횞 36 / 512 K 횞 18) Flow-Through SRAM with NoBL??Architecture

文件:783.8 Kbytes Page:33 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

封装/外壳:165-LBGA 包装:散装托盘 描述:IC SRAM 9MBIT PARALLEL 165FBGA 集成电路(IC) 存储器

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

同步 SRAM

INFINEON

英飞凌

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture

文件:504.58 Kbytes Page:28 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256 K x 36 / 512 K x 18) Flow-through SRAM with NoBL Architecture

文件:795.58 Kbytes Page:32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256 K 횞 36 / 512 K 횞 18) Flow-Through SRAM with NoBL??Architecture

文件:783.8 Kbytes Page:33 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

Synchronous SRAM

INFINEON

英飞凌

CY7C1357产品属性

  • 类型

    描述

  • 型号

    CY7C1357

  • 制造商

    Rochester Electronics LLC

  • 功能描述

    - Bulk

  • 制造商

    Cypress Semiconductor

更新时间:2026-3-14 13:48:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
CYPRESS/赛普拉斯
24+
TSOP44
11016
公司现货库存,支持实单
CYPRESS/赛普拉斯
2026+
QFP
117
原装正品,假一罚十!
Cypress(赛普拉斯)
2511
8484
电子元器件采购降本30%!原厂直采,砍掉中间差价
CYPRESS/赛普拉斯
23+
QFP100L
3000
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、
Cypress Semiconductor Corp
25+
100-LQFP
9350
独立分销商 公司只做原装 诚心经营 免费试样正品保证
ADI
23+
QFP
8000
只做原装现货
Cypress Semiconductor Corp
24+25+
16500
全新原厂原装现货!受权代理!可送样可提供技术支持!
CYPRESS/赛普拉斯
23+
QFP
50000
全新原装正品现货,支持订货
CYRESS?
23+
TQFP
2500
绝对全新原装!现货!特价!请放心订购!
Cypress
25+
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