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CY7C1352价格
参考价格：￥34.1996
型号：CY7C1352G-133AXC 品牌：Cynergy 3 备注：这里有CY7C1352多少钱，2026年最近7天走势，今日出价，今日竞价，CY7C1352批发/采购报价，CY7C1352行情走势销售排行榜，CY7C1352报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C1352 | 256K x18 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to e | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C1352 | 256K x18 Pipelined SRAM with NoBL Architecture | INFINEON 英飞凌 | | |
256K x18 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to e | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x18 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to e | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x18 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to e | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x18 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to e | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Pipilined SRAm with NoBL Architecture Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Pipilined SRAm with NoBL Architecture Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Pipilined SRAm with NoBL Architecture Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Pipilined SRAm with NoBL Architecture Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Pipilined SRAm with NoBL Architecture Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Pipilined SRAm with NoBL Architecture Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Pipilined SRAm with NoBL Architecture Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256Kx18) Pipelined SRAM with NoBL™ Architecture | INFINEON 英飞凌 | | ||
4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture 文件：330.48 Kbytes Page：12 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K 횞 18) Pipelined SRAM with NoBL??Architecture 文件：538.12 Kbytes Page：20 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K x 18) Pipelined SRAM with NoBL??Architecture 文件：555.33 Kbytes Page：21 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture 文件：330.48 Kbytes Page：12 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K 횞 18) Pipelined SRAM with NoBL??Architecture 文件：538.12 Kbytes Page：20 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K x 18) Pipelined SRAM with NoBL??Architecture 文件：555.33 Kbytes Page：21 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：托盘托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture 文件：330.48 Kbytes Page：12 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
IC SRAM 4.5M PARALLEL 100TQFP | INFINEON 英飞凌 | | ||
4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture 文件：330.48 Kbytes Page：12 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture 文件：330.48 Kbytes Page：12 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture 文件：330.48 Kbytes Page：12 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture 文件：330.48 Kbytes Page：12 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture 文件：330.48 Kbytes Page：12 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture 文件：330.48 Kbytes Page：12 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C1352产品属性
- 类型
描述
- 型号
CY7C1352
- 制造商
Cypress Semiconductor
- 功能描述
SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 5ns 100-Pin TQFP
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Cypress |
23+ |
100-TQFP |
65600 |
||||
CYPRESS |
2015+ |
TQFP |
19889 |
一级代理原装现货,特价热卖! |
|||
CY |
25+23+ |
N/A |
23288 |
绝对原装正品现货,全新深圳原装进口现货 |
|||
CYPRESS |
22+ |
TQFP |
8000 |
原装正品支持实单 |
|||
CY |
QFP100 |
98+ |
18 |
全新原装进口自己库存优势 |
|||
Cypress(赛普拉斯) |
21+ |
TQFP-100 |
30000 |
只做原装,质量保证 |
|||
CYPRES |
25+ |
QFP |
4500 |
全新原装、诚信经营、公司现货销售! |
|||
Cypress |
22+ |
52PLCC (19.13x19.13) |
9000 |
原厂渠道,现货配单 |
|||
CYPRESS |
24+ |
QFP |
1850 |
||||
Cypress Semiconductor Corp |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
CY7C1352芯片相关品牌
CY7C1352规格书下载地址
CY7C1352参数引脚图相关
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2019-3-29
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