CY7C1352价格

参考价格:¥34.1996

型号:CY7C1352G-133AXC 品牌:Cynergy 3 备注:这里有CY7C1352多少钱,2025年最近7天走势,今日出价,今日竞价,CY7C1352批发/采购报价,CY7C1352行情走势销售排行榜,CY7C1352报价。
型号 功能描述 生产厂家&企业 LOGO 操作
CY7C1352

256Kx18PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1352isa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352isequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredtoe

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx18PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1352isa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352isequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredtoe

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx18PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1352isa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352isequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredtoe

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx18PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1352isa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352isequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredtoe

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx18PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1352isa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352isequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredtoe

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx18PipilinedSRAmwithNoBLArchitecture

FunctionalDescription TheCY7C1352Bisa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredto

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx18PipilinedSRAmwithNoBLArchitecture

FunctionalDescription TheCY7C1352Bisa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredto

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx18PipilinedSRAmwithNoBLArchitecture

FunctionalDescription TheCY7C1352Bisa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredto

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx18PipilinedSRAmwithNoBLArchitecture

FunctionalDescription TheCY7C1352Bisa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredto

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx18PipilinedSRAmwithNoBLArchitecture

FunctionalDescription TheCY7C1352Bisa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredto

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx18PipilinedSRAmwithNoBLArchitecture

FunctionalDescription TheCY7C1352Bisa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredto

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx18PipilinedSRAmwithNoBLArchitecture

FunctionalDescription TheCY7C1352Bisa3.3V256Kby18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredto

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

FunctionalDescription[1] TheCY7C1352Fisa3.3V,256Kx18synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1352FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBLArchitecture

4-Mbit(256Kx18)PipelinedSRAMwithNoBL™Architecture Features •PincompatibleandfunctionallyequivalenttoZBT™devices •Internallyself-timedoutputbuffercontroltoeliminate theneedtouseOE •ByteWritecapability •256Kx18commonI/Oarchitecture •3.3Vcorepowersupp

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBLArchitecture

4-Mbit(256Kx18)PipelinedSRAMwithNoBL™Architecture Features •PincompatibleandfunctionallyequivalenttoZBT™devices •Internallyself-timedoutputbuffercontroltoeliminate theneedtouseOE •ByteWritecapability •256Kx18commonI/Oarchitecture •3.3Vcorepowersupp

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBLArchitecture

4-Mbit(256Kx18)PipelinedSRAMwithNoBL™Architecture Features •PincompatibleandfunctionallyequivalenttoZBT™devices •Internallyself-timedoutputbuffercontroltoeliminate theneedtouseOE •ByteWritecapability •256Kx18commonI/Oarchitecture •3.3Vcorepowersupp

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBLArchitecture

4-Mbit(256Kx18)PipelinedSRAMwithNoBL™Architecture Features •PincompatibleandfunctionallyequivalenttoZBT™devices •Internallyself-timedoutputbuffercontroltoeliminate theneedtouseOE •ByteWritecapability •256Kx18commonI/Oarchitecture •3.3Vcorepowersupp

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBLArchitecture

4-Mbit(256Kx18)PipelinedSRAMwithNoBL™Architecture Features •PincompatibleandfunctionallyequivalenttoZBT™devices •Internallyself-timedoutputbuffercontroltoeliminate theneedtouseOE •ByteWritecapability •256Kx18commonI/Oarchitecture •3.3Vcorepowersupp

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBLArchitecture

4-Mbit(256Kx18)PipelinedSRAMwithNoBL™Architecture Features •PincompatibleandfunctionallyequivalenttoZBT™devices •Internallyself-timedoutputbuffercontroltoeliminate theneedtouseOE •ByteWritecapability •256Kx18commonI/Oarchitecture •3.3Vcorepowersupp

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBLArchitecture

4-Mbit(256Kx18)PipelinedSRAMwithNoBL™Architecture Features •PincompatibleandfunctionallyequivalenttoZBT™devices •Internallyself-timedoutputbuffercontroltoeliminate theneedtouseOE •ByteWritecapability •256Kx18commonI/Oarchitecture •3.3Vcorepowersupp

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBLArchitecture

4-Mbit(256Kx18)PipelinedSRAMwithNoBL™Architecture Features •PincompatibleandfunctionallyequivalenttoZBT™devices •Internallyself-timedoutputbuffercontroltoeliminate theneedtouseOE •ByteWritecapability •256Kx18commonI/Oarchitecture •3.3Vcorepowersupp

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBLArchitecture

4-Mbit(256Kx18)PipelinedSRAMwithNoBL™Architecture Features •PincompatibleandfunctionallyequivalenttoZBT™devices •Internallyself-timedoutputbuffercontroltoeliminate theneedtouseOE •ByteWritecapability •256Kx18commonI/Oarchitecture •3.3Vcorepowersupp

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

文件:330.48 Kbytes Page:12 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256K횞18)PipelinedSRAMwithNoBL??Architecture

文件:538.12 Kbytes Page:20 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

文件:555.33 Kbytes Page:21 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

封装/外壳:100-LQFP 包装:卷带(TR) 描述:IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路(IC) 存储器

ETC

知名厂家

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

文件:330.48 Kbytes Page:12 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256K횞18)PipelinedSRAMwithNoBL??Architecture

文件:538.12 Kbytes Page:20 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

文件:555.33 Kbytes Page:21 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

封装/外壳:100-LQFP 包装:托盘托盘 描述:IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路(IC) 存储器

ETC

知名厂家

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

文件:330.48 Kbytes Page:12 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

文件:330.48 Kbytes Page:12 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

文件:330.48 Kbytes Page:12 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

文件:330.48 Kbytes Page:12 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

文件:330.48 Kbytes Page:12 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

文件:330.48 Kbytes Page:12 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(256Kx18)PipelinedSRAMwithNoBL??Architecture

文件:330.48 Kbytes Page:12 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

CY7C1352产品属性

  • 类型

    描述

  • 型号

    CY7C1352

  • 制造商

    Cypress Semiconductor

更新时间:2025-6-24 11:47:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
CYPRESS
23+
QFP100
8650
受权代理!全新原装现货特价热卖!
CYRREES
20+
QFP
500
样品可出,优势库存欢迎实单
Cypress
23+
100-TQFP
65600
Cypress
0631
11
公司优势库存 热卖中!!
CYPRESS(赛普拉斯)
24+
LQFP100
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
CYPRESS/赛普拉斯
24+
QFP
9600
原装现货,优势供应,支持实单!
Cypress
100-TQFP
1800
Cypress一级分销,原装原盒原包装!
CYPRESS
05+
原厂原装
4376
只做全新原装真实现货供应
CYP
1948+
QFP
6852
只做原装正品现货!或订货假一赔十!
CY
24+
N/A
80000
只做自己库存,全新原装进口正品假一赔百,可开13%增

CY7C1352芯片相关品牌

  • AMPHENOL
  • CK-COMPONENTS
  • DDK
  • GLENAIR
  • MACOM
  • Mitsubishi
  • MOLEX6
  • Panasonic
  • POWERDYNAMICS
  • RHOMBUS-IND
  • TELEDYNE
  • YAMAICHI

CY7C1352数据表相关新闻