4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp

4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp

4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp

4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp

4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp

4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp

4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp

4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture • Pin compatible and functionally equivalent to ZBT™ devices\n• Internally self-timed output buffer control to eliminate\n   the need to use OE\n• Byte Write capability\n• 256K x 18 common I/O architecture\n• 3.3V core power supply (VDD)\n• 2.5V/3.3V I/O power supply (VDDQ)\n• Fast clock-to-output t;

4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • 3.3V core power supp

4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture

文件：330.48 Kbytes Page：12 Pages

4-Mbit (256 K 횞 18) Pipelined SRAM with NoBL??Architecture

文件：538.12 Kbytes Page：20 Pages

4-Mbit (256 K x 18) Pipelined SRAM with NoBL??Architecture

文件：555.33 Kbytes Page：21 Pages

4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture

文件：330.48 Kbytes Page：12 Pages

4-Mbit (256 K 횞 18) Pipelined SRAM with NoBL??Architecture

文件：538.12 Kbytes Page：20 Pages

4-Mbit (256 K x 18) Pipelined SRAM with NoBL??Architecture

文件：555.33 Kbytes Page：21 Pages

封装/外壳：100-LQFP 包装：托盘托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

IC SRAM 4.5M PARALLEL 100TQFP

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture

文件：330.48 Kbytes Page：12 Pages

4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture

文件：330.48 Kbytes Page：12 Pages

4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture

文件：330.48 Kbytes Page：12 Pages

4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture

文件：330.48 Kbytes Page：12 Pages

4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture

文件：330.48 Kbytes Page：12 Pages

4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture

文件：330.48 Kbytes Page：12 Pages

4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture

文件：330.48 Kbytes Page：12 Pages

256K x18 Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to e

256K x 18 Pipilined SRAm with NoBL Architecture

Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to

4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352F is equipped with the advanced No Bus Latency™ (NoBL™) logic required