128K x 32 Synchronous Pipelined Cache RAM

Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All

4-Mbit (128K x 32) Pipelined Sync SRAM

Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

4-Mbit (128K x 32) Pipelined Sync SRAM

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